1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a capacitor as a capacitive element in a wiring structure. In particular, the invention relates to a semiconductor integrated circuit device suitably applicable to an SRAM (Static Random Access Memory) recording data in a capacitor.
2. Description of Related Art
In recent years, semiconductor integrated circuit devices have been designed to lower a power supply voltage down to about 1.0 to 2.1 V. Along with this tendency, an attempt has been made to finely set various element sizes or wiring line widths. For example, a memory cell size is reduced, and a wiring line connected with the memory is narrowed in the SRAM. Such reduction in line width and memory cell size is effective in terms of high-speed operation because a resistance value of a wiring line connecting between elements is reduced. Conversely, there is a possibility that a value of a parasitic capacitance of a wiring line increases to affect element characteristics. For example, an SRAM cell composed of six MOS transistors Q1 to Q6 of FIG. 14 stores data by use of parasitic capacitances (hereinafter, referred to as “node capacitances”) of wiring lines N1 and N2 for cross-connecting between gate terminals and drain terminals of a pair of driving transistors Q3 and Q4 that turn on/off contrarily to each other (hereinafter, in this specification, the wiring lines N1 and N2 are referred to as “node wiring lines”, and the node wiring lines imply a line connected with a node where drain terminals of a load transistor Q1 and the driving transistor Q3 are connected, and a line connected with a node where drain terminals of a load transistor Q2 and the driving transistor Q4 are connected). However, a diffusion layer (gate area) constituting the node capacitance is reduced as the memory cell size or line width is reduced. This reduces the node capacitance as well to incur a soft error. Incidentally, the term “soft error” means that data charges accumulated in a node capacitance escape toward a semiconductor substrate side when a memory cell is applied with α line or neutron beam, resulting in a data loss.
To overcome such a soft error, a technique disclosed in Japanese Unexamined Patent Publication No. 10-163440 aims at partially laminating respective node wiring lines (in the illustrated example of FIG. 14, node wiring lines N1 and N2) of a pair of driving transistors constituting a memory cell via an insulating layer. Then, a capacitor is formed in the laminated portion to thereby increase a parasitic capacitance of the node wiring lines, that is, the node capacitance. Hence, an amount of accumulated data charges increases along with the increase in node capacitance, so an SRAM that is highly resistant to the soft error can be obtained without increasing a memory size.
Further, a technique disclosed in Japanese Unexamined Patent Publication No. 2002-324855 aims at forming a trench in an insulating film formed on a semiconductor substrate and embedding a conductive film in the trench to form a node wiring line for the purpose of increasing a node capacitance. Further, Japanese Unexamined Patent Publication No. 2002-324855 discloses a technique of forming a plug-like first electrode in a part of the node wiring line, exposing an upper end of the first electrode by a desired height, and forming a capacitive insulating film and a second electrode to cover the exposed portion. With the technique of Japanese Unexamined Patent Publication No. 2002-324855, a capacitor is formed using upper and side surfaces of the first electrode, so an area of the capacitor opposing the second electrode can be increased, which is effective for increasing a node capacitance. In addition, the capacitive insulating film and the second electrode have the flat surface on the first electrode, making it possible to form the capacitive insulating film constituting the capacitor with a uniform thickness and improve a reliability of the capacitor.
With a similar technique as disclosed in Soft Error Immune 0.64 μm2 SRAM Cell with MIM Node Capacitor by 65 nm CMOS Technology for Ultra High Speed SRAM 0-7803-7873-3/03/$17.00(c)2003IEEE (hereinafter, reffered to as non-patent document 1), a trench is formed between a pair of node wiring lines formed in an insulating film as in Japanese Unexamined Patent Publication No. 2002-324855. A capacitive insulating film covers the trench, and a conductive film as the second electrode is embedded in the trench, so a capacitor is formed between a pair of node wiring lines and the second electrode. With this technique, the second electrode is formed to cover a trench formed in the insulating film. Hence, no node wiring line protrudes from the insulating film, and this technique is effective for leveling the surface as compared with the technique of Japanese Unexamined Patent Publication No. 2002-324855.
The technique of Japanese Unexamined Patent Publication No. 10-163440 requires that node wiring lines of a pair of driving transistors be laminated. As a result, the node wiring lines of two layers should be laminated. Thus, a node wiring pattern should be changed as compared with an existing SRAM where both node wiring lines are formed in the same layer. Further, a step of forming a contact for connecting a node wiring line formed in an upper layer with a transistor is necessary to increase the number of steps. In addition, a capacitor is formed only at intersections of the two node wiring lines, so it is difficult to secure a large area for an opposing electrode, and limitations are imposed on an increase of the node capacitance.
With the technique of Japanese Unexamined Patent Publication No. 2002-324855, both the node electrodes of a pair of driving transistors are formed in the same layer, so a node capacitance can be increased without changing a node wiring pattern of the existing SRAM. Further, according to both the techniques of Japanese Unexamined Patent Publication No. 2002-324855 and Non-Patent Document 1, a capacitor is formed between the upper and side surfaces of the node wiring line and a second electrode formed to cover the upper and side surfaces. Hence, the above techniques are effective for increasing an area of the node wiring lines to increase a node capacitance of the capacitor. However, according to both the techniques of Japanese Unexamined Patent Publication No. 2002-324855 and Non-Patent Document 1, a capacitor is formed only using the node wiring lines and the second electrode. Thus, an area of the capacitor opposing the electrode, which influences a node capacitance, depends on an area of the node wiring lines. Thus, in the case of reducing the node line width, the area of the capacitor opposing the electrode is reduced, whish is disadvantageous in terms of increasing the node capacitance. Further, according to the technique of Non-Patent Document 1, a second electrode is formed only in a part of the memory cell, so there is a difference in height between the area having the second electrode and the rest. There is a fear that disconnection of a wiring line formed in an upper layer occurs. In particular, if plural second electrodes are independently formed in one memory cell, a difference in height occurs between the respective second electrodes and their peripheral portions, and the total length thereof is considerably long.
Further, after the production of a semiconductor integrated circuit device, various characteristic inspections are executed. For example, in the case of executing a CDM (Charged Device Model) inspection to inspect with stand voltage, the semiconductor integrated circuit device is charged with generated static electricity. Thus, the SRAM obtained by forming a capacitance electrode in the node wiring lines via a thin capacitance insulating film to give a node capacitance is charged. Furthermore, the capacitance electrode is simultaneously charged to incur discharge with node wiring lines, power supply lines, or ground lines, with the result that the capacitance insulating film suffers an electrostatic discharge damage. The electrostatic discharge damage of the capacitance insulating film causes short-circuiting between the capacitance electrode and the node wiring lines to disable the operation of the SRAM. Even if not short-circuited, the node capacitance is lost to lower the foregoing resistance to soft error.